ByLocation: Bengaluru, Karnataka, India
Minimum Qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience with ARM-based SoCs, interconnects, and ASIC methodology
Preferred Qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering
- 3 years of experience with IP design for clocking, interconnects, peripherals
- Experience with methodologies for low power estimation, timing closure, synthesis
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)
About the job: As a RTL Design Engineer at Google, you’ll be part of a team that designs and builds the hardware, software, and networking technologies powering Google’s services. From circuit design to large system design, you’ll be involved in every stage, shaping the machinery that goes into our cutting-edge data centers, impacting millions of users worldwide.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Your role will contribute to this mission by combining Google AI, Software, and Hardware to create radically helpful experiences, making computing faster, seamless, and more powerful.
Responsibilities:
- Define block level design documents including interface protocol, block diagram, transaction flow, and pipelines.
- Perform RTL development, coding, debugging in Verilog, SystemVerilog, and conduct function/performance simulation debug as well as Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Engage in test plan and coverage analysis at both block and SoC-level verification.
- Collaborate effectively with multi-disciplined and multi-site teams.
Apply now: RTL Design Engineer at Google
