ByJob Title: Design Verification Engineer, Silicon Engineering
Location: Bengaluru, Karnataka, India
Minimum Qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience verifying digital logic at the Register Transfer Logic (RTL) level using SystemVerilog and Formal Verification Techniques.
- Experience with verification techniques, SystemVerilog Assertions (SVA), and assertion-based verification.
Preferred Qualifications:
- Master’s degree in Electrical Engineering or Computer Science.
- Experience creating and using verification components and environments in a standard verification methodology like UVM.
- Knowledge of Interconnect Protocols (e.g., AXI, ACE, CHI, CCIX, CXL).
- Familiarity with one or more of the following areas:
- Memory Management
- Cache Hierarchies
- Coherency
- DDR/LPDDR
- PCIe
- Packet Processors
About the Role:
This role involves working as part of a diverse team developing custom silicon solutions that will shape the future of Google’s hardware products. You’ll be contributing to innovations that power widely loved products, pushing boundaries to deliver high-performance, efficient, and integrated hardware experiences.
Responsibilities:
- Plan and execute the verification of next-generation configurable interconnect, memory management, power controllers, and pervasive IP.
- Develop and improve constrained-random verification environments using SystemVerilog and UVM, or perform formal verification with SVA and leading formal tools.
- Create cross-language tools and scalable verification methodologies.
- Write coverage measures for stimulus and corner cases, debug tests with design engineers to ensure functionally correct designs.
- Close coverage measures to identify verification gaps and track progress towards tape-out.
To Apply:
You can apply for this role via the following link: HIRING DESIGN VERIFICATION ENGINEER
