FACEBOOK IS HIRING ASIC ENGINEER, DESIGN

Role Overview:

Facebook is seeking talented ASIC Design Engineers to join their Infrastructure organization in Bangalore, India. This position involves developing world-class System on Chip (SoC) and Intellectual Property (IP) for data center applications. The role requires deep expertise in micro-architecture, RTL development, and close collaboration with various teams to ensure the design meets timing and power requirements.

Key Responsibilities:

• Micro-Architecture Development: Design and develop micro-architectures for complex systems.
• RTL Development: Create RTL code using Verilog, System Verilog, and High-Level Synthesis (HLS).
• Design Optimization: Perform Lint, Clock Domain Crossing (CDC) analysis, Synthesis, and Power Optimization.
• IP Integration: Identify, select, and integrate soft and hard IP into the design.
• Collaboration: Work closely with verification and emulation teams to develop test plans and debug issues. Collaborate with implementation teams to ensure design closure on timing and power.

Minimum Qualifications:

• Education: Bachelor’s degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.
• Experience:
  • At least 3+ years in silicon development.
  • Proficiency in Verilog or System Verilog.
  • Expertise (3+ years) in one of the following areas:
    • Micro-architecture and RTL development for complex control and data path IPs.
    • SoC Micro-architecture, Design, and Integration.
    • Implementation and Power Methodology development.

Preferred Qualifications:

• Experience in data path development.
• Experience with Synthesis and Timing Closure.

Application: Interested candidates can apply ASIC Design Engineer at Facebook.